Register Description R820T2 (Rafael Micro) - 4

Read Mode
When the slave address matches the I2C device ID with read control bit, data are immediately transferred after ack command. Reading data transmission begins from core register 0 to final register until “P”(STOP) occurs. The data is transmitted from LSB to MSB, and the data of register 0 (0x96) is fixed as reference check point for read mode. Figure 1-3 : The Typical Read Mode Sequence {Chip ID,0} Data in Data in Data in Data in S A A A A A EE. A/ Ā P Ex:00110101 Register 0 Register 1 Register 2 Register 3 S :From Master to Slave A :Acknowledge (SDA low) S :Start P :Stop Ā NO Acknowledge (SDA high) Figure 1-4 : An Example of Read Mode Procedure SCL SDA CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 4