Register Description R820T2 (Rafael Micro) - 9

Reg R/W Bitmap Symbol Description
Clock out pin control R/W [4] CLK_OUT_ENB 0: clk output on
R15
1: off
0x0F
AGC clk control R/W [1] CLK_AGC_ENB 0: internal agc clock on 1: off PLL to Mixer divider number control 000: mixer in = vco out /2 R/W [7:5] SEL_DIV[3:0] 001:mixer in = vco out / 4 010: mixer in = vco out / 8 011:mixer in = vco out PLL Reference frequency Divider
R16
R/W [4] REFDIV 0 -> fref=xtal_freq
0x10
1 -> fref=xta_freql / 2 (for Xtal >24MHz) Internal xtal cap setting 00->no cap ; R/W [1:0] CAPX[1:0] 01->10pF 10->20pF ; 11->30pF PLL analog low drop out regulator switch 00: off
R17
R/W [7:6] PW_LDO_A[1:0] 01: 2.1V
0x11
10: 2.0V 11: 1.9V PLL integer divider number input Si2c
R20
R/W [7:6] SI2C[1:0] Nint=4*Ni2c+Si2c+13
0x14
PLL divider number Ndiv = (Nint + Nfra)*2 R/W [5:0] NI2C[5:0] PLL integer divider number input Ni2c
R21
R/W [7:0] SDM_IN[7:0] PLL fractional divider number input SDM[16:1]
0x15
Nfra=SDM_IN[16]*2^-1+SDM_IN[15]*2^-2+E+SDM_IN[2]
R22
R/W [7:0] SDM_IN[7:0] *2^-15+SDM_IN[1]*2^-16
0x16
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