Datasheet SN74LVC1G16 (Texas Instruments) - 7
| Производитель | Texas Instruments |
| Описание | One-channel 1.65V-to-5.5V inverter with open-drain outputs and Schmitt-trigger inputs |
| Страниц / Страница | 30 / 7 — SN74LVC1G16. www.ti.com. 6 Parameter Measurement Information. TEST. … |
| Формат / Размер файла | PDF / 1.2 Мб |
| Язык документа | английский |
SN74LVC1G16. www.ti.com. 6 Parameter Measurement Information. TEST. VLOAD. VCC. Figure 6-1. Load Circuit for Open-Drain Outputs

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SN74LVC1G16 www.ti.com
SCLSA29B – OCTOBER 2024 – REVISED MAY 2025
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns. The outputs are measured individually with one input transition per measurement.
TEST S1 RL CL ΔV VLOAD
tPLZ, tPZL CLOSED 500Ω 50pF 0.3V 2×VCC
VCC Vt RL CL ΔV VLOAD
1.8V ± 0.15V VCC/2 1kΩ 15pF/30pF 0.15V 2×VCC 2.5V ± 0.2V VCC/2 500Ω 15pF/30pF 0.15V 2×VCC 3.3V ± 0.3V 1.5V 500Ω 15pF/50pF 0.3V 6V 5.0V ± 0.5V 1.5V 500Ω 15pF/50pF 0.3V 6V VLOAD Test VCC Point Input Vt Vt S1 0 V R From Output L t (1) (2) PLZ tPZL Under Test VOH C (1) L RL Output 50% Waveform 1 VOL + V VOL (1) C (2) (1) L includes probe and test-fixture capacitance. tPZL tPLZ
Figure 6-1. Load Circuit for Open-Drain Outputs
VOH Output 50% Waveform 2 VOL + V VOL (1) tPLZ is the same as tdis. (2) tPZL is the same as ten.
Figure 6-2. Voltage Waveforms Propagation Delays
Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74LVC1G16 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Switching Characteristics 5.7 Typical Characteristics 6 Parameter Measurement Information 7 Overview 8 Functional Block Diagram 9 Detailed Description 9.1 Feature Description 9.1.1 Open-Drain CMOS Outputs 9.1.2 CMOS Schmitt-Trigger Inputs 9.1.3 Clamp Diode Structure 10 Application and Implementation 10.1 Application Information 10.2 Typical Application 10.2.1 Design Requirements 10.2.1.1 Power Considerations 10.2.1.2 Input Considerations 10.2.1.3 Output Considerations 10.2.2 Detailed Design Procedure 10.3 Application Curves 10.4 Power Supply Recommendations 10.5 Layout 10.5.1 Layout Guidelines 10.5.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Revision History 13 Mechanical, Packaging, and Orderable Information