Datasheet TB9084FTG (Toshiba) - 5

TB9084FTG
6. Pin Description Table 6.1 Pin Description Pull-up/down No. Name I/O Function Resistance
1 LWO OUT Gate driver output (W phase low-side) Pull-down to LS 2 LVO OUT Gate driver output (V phase low-side) Pull-down to LS 3 LUO OUT Gate driver output (U phase low-side) Pull-down to LS 4 LS IN Reference input for low-side gate drivers - Output for driving FET for reverse polarity 5 RPPO OUT - protection Power 6 VCP Charge pump voltage supply Pull-down to VB 7 CP2B I/O Charge pump 2nd stage bias voltage - 8 CP1B I/O Charge pump 1st stage bias voltage - 9 CP2SW OUT Charge pump 2nd stage drive output - 10 PGND GND Power ground - 11 CP1SW OUT Charge pump 1st stage drive output - Power - 12 VB External battery power supply supply 13 HWO OUT Gate driver output (W phase high-side) Pull-down to HWS Gate driver reference input (W phase high- - 14 HWS IN side source) 15 HVO OUT Gate driver output (V phase high-side) Pull-down to HVS Gate driver reference input (V phase high- - 16 HVS IN side source) 17 HUO OUT Gate driver output (U phase high side) Pull-down to HUS Gate driver reference input (U phase high- - 18 HUS IN side source) VDS detection input of 3-phase FET (high- 19 HS IN - side) 20 ALARM IN Gate driver emergency stop input Pull-up to VCC 21 HWI IN Gate driver input (W phase high-side) Pull-down to GND 22 HVI IN Gate driver input (V phase high-side) Pull-down to GND 23 HUI IN Gate driver input (U phase high-side) Pull-down to GND 6-input mode (Polarity during power-on: “L”) 24 LUI IN Pull-down to GND Gate driver input (U phase low-side) 6-input mode (Polarity during power-on: “L”) 25 LVI IN Pull-down to GND Gate driver input (V phase low-side) 6-input mode (Polarity during power-on: “L”) 26 LWI IN Pull-down to GND Gate driver input (W phase low-side) 27 SCLK IN SPI clock input Pull-down to GND 28 NCS IN SPI chip select Pull-up to VCC 29 SI IN SPI input Pull-down to GND 30 SO OUT SPI output - 31 NDIAG OUT Error output - Power 32 VCC External 5V/3.3V power supply supply - 33 GND GND Analog, digital ground - 34 AMP_O OUT Current sensing amplifier output - 35 AMP_N IN Current sensing amplifier (-) input - 36 AMP_P IN Current sensing amplifier (+) input - © 2 025 5 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE