Datasheet AD9625 (Analog Devices) - 23

Data Sheet AD9625 0 1.5 2500MSPS fIN1 = 228.5MHz AT –7.0dBFS f –20 IN2 = 231.5MHz AT –7.0dBFS 1.0 SFDR = 76.7dBc S) –40 0.5 F B ) B E (d D –60 LS 0 U L ( IT IN MPL –80 A –0.5 –100 –1.0 –120 –1.5 0 250 500 750 1000 1250
336
0 1024 2048 3072 4096
343
FREQUENCY (MHz)
1814- 1
CODES
1814- 1 Figure 43. Two Tone FFT Plot at 2.5 GSPS, fIN1 = 228.5 MHz and Figure 44. Integral Nonlinearity (INL), ±1.0 LSB at 2.5 GSPS fIN2 = 231.5 MHz at AIN, −7.0 dBFS (SFDR = 76.7 dBc) Rev. B | Page 23 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE