Datasheet LTC6943 (Analog Devices) - 5

LTC6943
TEST CIRCUITS Test Circuit 1. Leakage Current Test Test Circuit 2. RON Test
(6, 11, 5, 16) (7, 12, 4, 13) (6, 11, 5, 16) (7, 12, 4, 13) NOTE: TO OPEN SWITCHES, A S1 AND S3 PIN 14, SHOULD BE CONNECTED + TO V–. TO OPEN S2, S4, THE V + IN C 0V TO 10V OSC PIN 14 SHOULD BE (9, 10, 1, 2) CONNECTED TO V+ C (9, 10, 1, 2) OSC 100µA to 1mA A 6943 • TC01 CURRENT SOURCE 6943 • TC02
Test Circuit 3. Oscillator Frequency, fOSC Test Circuit 4. CMRR Test
6 7 VOUT V– (TEST PIN) 1 15 8 9 V+ COSC 3 14 + LTC6943 CAPACITORS ARE 1µF 1µF NOT ELECTROLYTIC 4 10 5 + IV 11 12 6943 • TC03 + V– ≤ VCM ≤ V+ VCM CMRR = 20 LOG ( VOUT ) NOTE: FOR OPTIMUM CMRR, THE COSC SHOULD BE LARGER THAN 0.0047µF, AND THE SAMPLING CAPACITOR ACROSS PINS 9 AND 10 SHOULD BE PLACED OVER A SHIELD TIED TO PIN 8 6943 • TC04
U U W U APPLICATIO S I FOR ATIO Common Mode Rejection Ratio (CMRR)
1/2 LTC6943 The LTC6943, when used as a differential to single-ended 6 7 converter rejects common mode signals and preserves differential voltages (Figure 1). Unlike other techniques, C+ 9 the LTC6943’s CMRR does not degrade with increasing + + V C V C common mode voltage frequency. During the sampling D S D H mode, the impedance of Pins 1, 2 (and 9, 10) should be C– 10 balanced, otherwise, common mode signals will appear differentially. The value of the CMRR depends on the value 11 12 of the sampling and holding capacitors (CS, CH) and on the + V sampling frequency. Since the common mode voltages CM are not sampled, the common mode signal frequency can well exceed the sampling frequency without experiencing CS, CH ARE MYLAR OR POLYPROPYLENE aliasing phenomena. The CMRR of Figure 1 is measured 6943 • AI01 by shorting Pins 6 and 11 and by observing, with a
Figure 1. Differential to Single-Ended Converter
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