Dual bidirectional bus buffer
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Dual bidirectional bus buffer
Rev. 5 -5 May 2011 Product data sheet 1. General description
The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface between a normal I2C-bus and a range of other higher capacitance or different voltage bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications. The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I2C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels. The separation of the bidirectional I2C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal. 2. Features and benefits
Bidirectional data transfer of I2C-bus signals Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive buses 1 MHz operation on up to 20 meters of wire (see AN10658) Supply voltage range of 2.5 V to 15 V with I2C-bus logic levels on SX/SY side independent of supply voltage Splits I2C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths Low power supply current ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8 and TSSOP8 (MSOP8) NXP Semiconductors PCA9600
Dual bidirectional bus buffer 3. Applications
Interface between I2C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V) Interface between I2C-bus and SMBus (350 A) standard or Fm+ standard Simple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250 Interfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to 1 MHz Long distance point-to-point or multipoint architectures 4. Ordering information
Table 1. Ordering information Package Name ...
Цены
PCA9600D,118 на РадиоЛоцман.Цены — от 144 до 412 руб.
Буферы и линейные аппаратные драйверы FM+ BUS BUFFER
| Поставщик | Производитель | Наименование | Цена |
|---|---|---|---|
| 5 элемент | NXP | PCA9600D,118 | 144 руб. |
| ПМ Электроникс | NXP | PCA9600D,118 | от 158 руб. |
| Элитан | NXP | PCA9600D,118 | 412 руб. |
| Кремний | NXP | PCA9600D118 | по запросу |
| LifeElectronics | NXP | PCA9600D,118 | по запросу |
| Все 6 предложений от 5 поставщиков » | |||
Классификация производителя
Interface and connectivity > I2C > I2C voltage level translators
Варианты написания: PCA9600D118, PCA9600D 118
Выписка из документа:
PCA9600Dual bidirectional bus buffer
Rev. 5 -5 May 2011 Product data sheet 1. General description
The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface between a normal I2C-bus and a range of other higher capacitance or different voltage bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications. The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I2C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels. The separation of the bidirectional I2C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal. 2. Features and benefits
Bidirectional data transfer of I2C-bus signals Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive buses 1 MHz operation on up to 20 meters of wire (see AN10658) Supply voltage range of 2.5 V to 15 V with I2C-bus logic levels on SX/SY side independent of supply voltage Splits I2C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths Low power supply current ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standar...
- Серия: PCA9600 (4)
На английском языке: Datasheet NXP PCA9600DP
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