AD9601ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress ELECTRICAL rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. Dx0 Through Dx9 to DRGND −0.3 V to DRVDD + 0.3 V THERMAL RESISTANCE DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V The exposed paddle must be soldered to the ground plane for OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V the LFCSP package. Soldering the exposed paddle to the CLK+ to AGND −0.3 V to +3.6 V customer board increases the reliability of the solder joints, CLK− to AGND −0.3 V to +3.6 V maximizing the thermal capability of the package. VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V Table 6. SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V Package TypeθJAθJCUnit PDWN to AGND −0.3 V to +3.6 V 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W CSB to AGND −0.3 V to +3.6 V SCLK/DFS to AGND −0.3 V to +3.6 V Typical θJA and θJC are specified for a 4-layer board in still air. ENVIRONMENTAL Airflow increases heat dissipation, effectively reducing θJA. In Storage Temperature Range −65°C to +125°C addition, metal in direct contact with the package leads from Operating Temperature Range −40°C to +85°C metal traces, and through holes, ground, and power planes Lead Temperature 300°C reduces the θJA. (Soldering, 10 sec) Junction Temperature 150°C ESD CAUTION Rev. 0 | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
