link to page 10 link to page 10 link to page 10 link to page 10 link to page 11 link to page 11 link to page 17 link to page 11 link to page 11 AD7822/AD7825/AD7829CIRCUIT INFORMATION CIRCUIT DESCRIPTIONREFERENCE The AD7822/AD7825/AD7829 consist of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. These devices use a half-flash conversion technique where one R16 4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash 15DB7 ADC contains a sampling capacitor followed by 15 comparators R15DB6SW2 that compare the unknown input to a reference ladder to AVT/H 1DB514IN achieve a 4-bit result. This first flash (that is, coarse conversion) RSAMPLINGBTTDEU ETU RSDB4HOLDCAPACITORE provides the four MSBs. For a full 8-bit reading to be realized, COTP ISTP VGR14LOGICDB3DEOUOU DRI a second flash (that is, fine conversion) must be performed to 13REDB2 provide the four LSBs. The 8-bit word is then placed on the data R13DB1 output bus. DB01 Figure 6 and Figure 7 show simplified schematics of the ADC. R1 When the ADC starts a conversion, the track-and-hold goes TIMING AND into hold mode and holds the analog input for 120 ns. This is CONTROLLOGIC 007 the acquisition phase, as shown in Figure 6, when Switch 2 is in 21- 013 Position A. At the point when the track-and-hold returns to its Figure 7. ADC Conversion Phase track mode, this signal is sampled by the sampling capacitor, 120ns as Switch 2 moves into Position B. The first flash occurs at this TRACKHOLDTRACKHOLD instant and is then followed by the second flash. Typically, the CONVSTt2 first flash is complete after 100 ns, that is, at 220 ns; and the end t1 of the second flash and, hence, the 8-bit conversion result is EOC available at 330 ns (minimum). The maximum conversion time CS is 420 ns. As shown in Figure 8, the track-and-hold returns to t3 track mode after 120 ns and starts the next acquisition before RD the end of the current conversion. Figure 10 shows the ADC 008 VALID transfer function. DB0 TO DB7DATA 1321- 0 Figure 8. Track-and-Hold Timing REFERENCETYPICAL CONNECTION DIAGRAM Figure 9 shows a typical connection diagram for the AD7822/ AD7825/AD7829. The AGND and DGND are connected R1615DB7 together at the device for good noise suppression. The parallel R15DB6 interface is implemented using an 8-bit data bus. The end of SW2A conversion signal (EOC) idles high, the falling edge of CONVST VT/H 1DB514INRSAMPLINGBTTDE ICU ETU RSDB4 initiates a conversion, and at the end of conversion the falling HOLDCAPACITORGPECOT ISTP VG edge of EOC is used to initiate an interrupt service routine R14LODB3DE13OUOUREDRI (ISR) on a microprocessor (see the Parallel Interface section for DB2R13 more details.) V DB1 REF and VMID are connected to a voltage source such as the AD780, and VDD is connected to a voltage source DB01 that can vary from 4.5 V to 5.5 V (see Table 5 in the Analog Input R1 section). When VDD is first connected, the AD7822/AD7825/ TIMING AND AD7829 power up in a low current mode, that is, power-down CONTROLLOGIC 006 mode, with the default logic level on the EOC pin on the 01321- AD7822 and AD7825 equal to a low. Ensure the CONVST line is Figure 6. ADC Acquisition Phase not floating when VDD is applied, because this can put the AD7822/AD7825/AD7829 into an unknown state. Rev. C | Page 10 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY CIRCUIT INFORMATION CIRCUIT DESCRIPTION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION ANALOG INPUT POWER-UP TIMES POWER VS. THROUGHPUT OPERATING MODES PARALLEL INTERFACE MICROPROCESSOR INTERFACING AD7822/AD7825/AD7829 TO 8051 AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x AD7822/AD7825/AD7829 TO ADSP-21xx INTERFACING MULTIPLEXER ADDRESS INPUTS AD7822 STANDALONE OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
