Data SheetAD96942.01.851.51.801.751.01.700.5)) B(W 1.65LS0ERL (W 1.60INPO–0.51.55–1.01.50–1.51.45–2.01.400250300350400450500550600650 122 102420483072409651206144716881929216 18 SAMPLE RATE (MSPS)10240112641228813312143361536016384 1 14808- OUTPUT CODE 14808- Figure 24. INL, f Figure 27. Power Dissipation vs. Sample Rate (fS) IN = 10.3 MHz 1.00AIN = –1dBFS SNRFS = 65.94dB0.8–20SFDR = 89.01dBFS0.6–400.4S) F–60B0.2B) SE (dLD(0–80U ITDNL –0.2–100MPL A–0.4–120–0.6–140–0.8–1.0–1600–125–75–252575125 123 102420483072409651206144716881929216 19 FREQUENCY (MHz)10240112641228813312143361536016384 1 14808- OUTPUT CODE 14808- Figure 25. DNL, f Figure 28. DDC Mode (4 DDCs; Decimate by 2; L = 2, M = 4, and F = 4) IN = 10.3 MHz with fIN = 305 MHz 06000AIN = –1dBFS SNRFS = 71.80dB–20SFDR = 98.27dBFS5000–40S)S4000FT–60BHI FE (d D–80UR O3000ITBE–100MPLNUM2000A–1201000–140–16000555055551234567891017.37.57.62.N – 9N – 8N – 7N – 6N – 5N – 4N – 3N – 2N – 1N +N +N +N +N +N +N +N +N +–62.–42.–22. 124 N – 10N + 120 FREQUENCY (MHz)CODE 14808- 14808- Figure 26. Input Referred Noise Histogram Figure 29. DDC Mode (4 DDCs; Decimate by 4; L = 1, M = 4, and F = 8) with fIN = 305 MHz Rev. 0 | Page 17 of 101 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE
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