Datasheet AD7722 (Analog Devices) - 23

AD7722
the analog and digital systems. Fast switching signals like clocks should be shielded with their associated ground to avoid radiating
14 AVDD1 100nF
noise to other sections of the board, and clock signals should
10 AGND1
never be routed near the analog inputs.
5V
Avoid running digital lines under the device as these will couple
20 AVDD
noise onto the die. The analog ground plane should be allowed
100nF 10 F 100nF 19 AGND
to run under the AD7722 to shield it from noise coupling. The
AV
power supply lines to the AD7722 should use as large a trace as
23 DD 100nF
possible (preferably a plane) to provide a low impedance path
25 AGND
and reduce the effects of glitches on the power supply line. Avoid crossover of digital and analog signals. Traces on opposite
10 39 DV
sides of the board should run at right angles to each other. This
DD 1nF 100nF 10 F 100nF
will reduce the effects of feedthrough through the board.
5 DGND 28 DGND
Figure 29. Power Supply Decoupling –22– REV. B Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History