Datasheet KSZ8794CNX (Microchip) - 35

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KSZ8794CNX
For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows which port the MLD packet was received on. This is achieved by setting Register 12 Bit[1]. 3.6.7 PORT MIRRORING SUPPORT The KSZ8794CNX supports “port mirror” as described in the following: 3.6.7.1 “Receive Only” Mirror on a Port All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “RX sniff,” and Port 4 is programmed to be the “sniffer port”. A packet, received on Port 1, is destined to Port 3 after the internal look-up. The KSZ8794CNX will forward the packet to both Port 3 and Port 4. KSZ8794CNX can optionally for- ward even “bad” received packets to Port 3. 3.6.7.2 “Transmit Only” Mirror on a Port All the packets transmitted on the port will be mirrored on the Sniffer Port. For example, Port 1 is programmed to be “TX sniff,” and Port 4 is programmed to be the “sniffer port”. A packet, received on any of the Ports, is destined to Port 1 after the internal look-up. The KSZ8794CNX will forward the packet to both Ports 1 and 4. 3.6.7.3 “Receive and Transmit” Mirror on Two Ports All the packets received on Port A and transmitted on Port B will be mirrored on the sniffer port. To turn on the “AND” feature, set Register 5 bit[0] to Bit[1]. For example, Port 1 is programmed to be “RX sniff,” Port 2 is programmed to be “TX sniff,” and Port 4 is programmed to be the “sniffer port”. A packet, received on Port 1, is destined to Port 3 after the internal look-up. The KSZ8794CNX will forward the packet to Port 4 only because it does not meet the “AND” condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8794CNX will forward the packet to both Port 2 and Port 4 because it does meet the “AND” condition. Multiple ports can be selected to be “RX sniffed” or “TX sniffed.” Any port can be selected to be the “sniffer port.” All these per port features can be selected through the Port Control 1 Register. 3.6.8 VLAN SUPPORT The KSZ8794CNX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. The KSZ8794CNX provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look- up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up when 802.1q is enabled by the global Register 5 control 3 Bit[7]. In the VLAN mode, the look-up process starts from VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. Table 3-15 describes the different actions in different situations of DA and FID+DA in the static MAC table and dynamic MAC table after the VLAN table finishes a look-up action. FID+SA is used for learning purposes. Table 3-16 also describes learning in the dynamic MAC table when the VLAN table has done a look-up in the static MAC table without a valid entry.
TABLE 3-15: FID+DA LOOK-UP IN VLAN MODE DA Found in FID+DA Found in Static MAC Use FID Flag? FID Match? Dynamic MAC Action Table? Table?
No Don’t Care Don’t Care No Broadcast to the membership ports defined in the VLAN Table Bits[11:7]. No Don’t Care Don’t Care Yes Send to the destination port defined in the Dynamic MAC Address Table Bits[58:56]. Yes 0 Don’t Care Don’t Care Send to the destination port(s) defined in the Static MAC Address Table Bits[52:48]. Yes 1 No No Broadcast to the membership ports defined in the VLAN Table Bits[11:7].  2016 Microchip Technology Inc. DS00002134A-page 35 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines