Datasheet AD8432 (Analog Devices) - 25

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Data Sheet AD8432 EVALUATION BOARD
Figure 73 is a photo of the AD8432 evaluation board. Completely
Input Termination
assembled and pretested, the board provides convenient and fast The AD8432 features active input termination and boards are verification of system design and to assess the performance of shipped for 50 Ω. The input impedance is determined by the LNA the AD8432 under user-specific operating conditions. The gain, and the feedback resistors RFB1 and RFB2 (see the schematic in remainder of this section describes the operation and construction Figure 80) and source impedance (refer to the Theory of Operation of the board. section and Table 7). CFB provides the necessary ac coupling Figure 74 through Figure 79 are various artwork and assembly between the input and output when using active termination; a views and Figure 80 shows the schematic diagram. The board 0.1 μF capacitor is recommended. The RFB and CFB network provides access to the inputs, the outputs, and the gain settings. presents a load to the OPL; if needed, an equivalent load at OPH As shipped, the board is configured for a gain of 21 dB and 50 Ω balances the differential output. input termination. Multiple combinations of gain and impedance Switches CLAMP1 and CLAMP2 connect the input clamping matching are available to the user. diodes (IND1 and IND2) across the signal path. The diodes provide input overvoltage protection in applications where fast transient pulses exceeding 5.5 V or less than –0.6 V are present. Clamping diodes enable faster overdrive recovery times, especially at the lowest gain (12.04 dB). Fast transients are usually not fatal to the device, which features ESD protection in any event.
Setting the Amplifier Gain
The violet test loops OPnn, GOnn and GMnn and Resistors R1–R4 and Resistors R9–R12 are provided for gain adjustment. Install 0 Ω resistors to reduce gain, leaving the positions open to increase gain. As shipped, the evaluation board is configured for G = 21 dB (12×). Table 8 lists the configuration for the four available LNA gain values.
Table 8. Gain Setting Configuration GAIN dB(×) LNA1 LNA2 8(4) 18(8) 21(12) 24(16)
R1 R9 Y1 Y1 open open 73 0 R2 R10 Y1 open Y1 open 1- 834 0 R3 R11 Y1 open Y1 open Figure 73. Evaluation Board R4 R12 Y1 Y1 open open
CONNECTION AND OPERATION
1 Y = Install 0 Ω.
Power Supply Output
The AD8432 requires only a single 5 V supply connected to the The 4-pin headers PR1OUT and PR2OUT are placed close to +5V red test loop and black test loop GND next to it. Separate the AD8432, and provide a way for monitoring the differential power pins are provided for the two LNA channels, but the two output or the single-ended output using a high impedance amplifier sections are wired together and rf-decoupled by small differential probe. The two inner pins of the headers are connected inductors as a precaution. The remaining red test loops are for to OPL/OPH, and the two outer pins of the headers are connected pin probing as necessary. Should the need for amplifier isolation to ground. arise, simply un-power the unneeded amplifier by removing L3 or L4. (Refer to Figure 74 and Figure 80. Rev. D | Page 25 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION LOW NOISE AMPLIFIER (LNA) GAIN SETTING TECHNIQUE ACTIVE INPUT RESISTANCE MATCHING APPLICATIONS INFORMATION TYPICAL SETUP I/Q DEMODULATION FRONT END DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION EVALUATION BOARD CONNECTION AND OPERATION Power Supply Input Termination Setting the Amplifier Gain Output SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES NOTES