RX65N Group, RX651 Group 1. Overview Table 1.1Outline of Specifications (7/10)ClassificationModule/FunctionDescription Communication Serial communications 13 channels (SCIg: 10 channels + SCIh: 1 channel + SCIi: 2 channels) function interfaces SCIg, SCIh, SCIi (SCIg, SCIh, SCIi) Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Start-bit detection: Level or edge detection is selectable. Simple I2C Simple SPI 9-bit transfer mode Bit rate modulation Double-speed mode SCIg, SCIh Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12 Event linking by the ELC (only on channel 5) SCIh Supports the serial communications protocol, which contains the start frame and information frame Supports the LIN format SCIi Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the transmission and reception unit I2C bus interface (RIICa) 3 channels (only channel 0 can be used in fast-mode plus) Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 1 Mbps (channel 0) Event linking by the ELC CAN module (CAN) 2 channels Compliance with the ISO11898-1 specification (standard frame and extended frame) 32 mailboxes per channel Serial peripheral 3 channels interface (RSPIc) RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Transit/receive data can be swapped in byte units Buffered structure Double buffers for both transmission and reception RSPCK can be stopped with the receive buffer full for master reception. Event linking by the ELC Quad serial peripheral 1 channel interface (QSPI) Connectable with serial flash memory equipped with multiple input and output lines (i.e. for single, dual, or quad operation) Programmable bit length and selectable active sense and phase of the clock signal Sequential execution of transfer LSB or MSB first is selectable R01DS0276EJ0230 Rev.2.30 Page 8 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
