HT45F5Q-3HT45F5Q-3Battery Charger Flash MCUBattery Charger Flash MCUMnemonicDescriptionCycles Flag AffectedData Move MOV A,[m] Move Data Memory to ACC 1 None MOV [m],A Move ACC to Data Memory 1Note None MOV A,x Move immediate data to ACC 1 None Bit Operation CLR [m].i Clear bit of Data Memory 1Note None SET [m].i Set bit of Data Memory 1Note None Branch Operation JMP addr Jump unconditionally 2 None SZ [m] Skip if Data Memory is zero 1Note None SZA [m] Skip if Data Memory is zero with data movement to ACC 1Note None SZ [m].i Skip if bit i of Data Memory is zero 1Note None SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None SIZ [m] Skip if increment Data Memory is zero 1Note None SDZ [m] Skip if decrement Data Memory is zero 1Note None SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None CALL addr Subroutine call 2 None RET Return from subroutine 2 None RET A,x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD [m] Read table (specific page or current page) to TBLH and Data Memory 2Note None TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR [m] Clear Data Memory 1Note None SET [m] Set Data Memory 1Note None CLR WDT Clear Watchdog Timer 1 TO, PDF CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF SWAP [m] Swap nibbles of Data Memory 1Note None SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None HALT Enter power down mode 1 TO, PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then up to two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 150 July 31, 2019 Rev. 1.00 151 July 31, 2019 Document Outline Features CPU Features Peripheral Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics High Speed Internal Oscillator – HIRC – Frequency Accuracy Low Speed Internal Oscillator Characteristics – LIRC Operating Frequency Characteristic Curves System Start Up Time Characteristics Input/Output Characteristics Memory Characteristics LVR Electrical Characteristics A/D Converter Electrical Characteristics D/A Converter Electrical Characteristics Operational Amplifier Electrical Characteristics Software Controlled LCD Driver Electrical Characteristics Power-on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0, IAR1 Memory Pointers – MP0, MP1 Bank Pointer – BP Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP, TBHP, TBLH Status Register – STATUS Emulated EEPROM Data Memory Emulated EEPROM Data Memory Structure Emulated EEPROM Registers Erasing the Emulated EEPROM Writing Data to the Emulated EEPROM Reading Data from the Emulated EEPROM Programming Considerations Oscillators Oscillator Overview System Clock Configurations Internal High Speed RC Oscillator – HIRC Internal 32kHz Oscillator – LIRC Operating Modes and System Clocks System Clocks System Operation Modes Control Registers Operating Mode Switching Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors Port A Wake-up I/O Port Control Registers Pin-shared Functions I/O Pin Structures READ PORT Function Programming Considerations Timer Modules – TM Introduction TM Operation TM Clock Source TM Interrupts TM External Pins Programming Considerations Compact Type TM – CTM Compact Type TM Operation Compact Type TM Register Description Compact Type TM Operation Modes Standard Type TM – STM Standard TM Operation Standard Type TM Register Description Standard Type TM Operation Modes Analog to Digital Converter A/D Converter Overview A/D Converter Register Description A/D Converter Data Registers – SADOL, SADOH A/D Converter Reference Voltage A/D Converter Input Signal A/D Converter Operation Conversion Rate and Timing Diagram Summary of A/D Conversion Steps Programming Considerations A/D Conversion Function A/D Conversion Programming Examples Battery Charge Module Battery Charge Module Registers Digital to Analog Converter Operational Amplifiers Universal Serial Interface Module – USIM SPI Interface I2C Interface UART Interface Software Controlled LCD Driver LCD Operation LCD Bias Current Control Cyclic Redundancy Check – CRC CRC Registers CRC Operation Interrupts Interrupt Registers Interrupt Operation External Interrupts Time Base Interrupts Multi-function Interrupts TM Interrupts A/D Converter Interrupt USIM Interrupt Interrupt Wake-up Function Programming Considerations Application Descriptions Introduction Functional Description Hardware Circuit Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 24-pin SSOP (150mil) Outline Dimensions 28-pin SSOP (150mil) Outline Dimensions
