Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 11

PRELIMINARY EZ-PD CCG6DF, CCG6SF Table 2. Pinout for CYPD6227-96BZXI
(continued)
Group Name Pin Name Port Pin Description
I2C_SDA_SCB1/P0.2 GPIO K9 SCB1 data for communicating with SoC or TBT controller/ GPIO I2C_SCL_SCB1/P0.3 GPIO H7 SCB1 clock for communicating with SoC or TBT controller / GPIO I2C_INT_EC/P1.2 GPIO F11 Embedded Controller interrupt / GPIO P2.4 GPIO D10 GPIO I2C_INT_TBT_P0/P0.4 GPIO L9 ThunderBolt interrupt for Port-0 / GPIO SWD_IO/P1.1 GPIO G8 Serial Wire Debug I/O / GPIO SWD_CLK/P1.0 GPIO F10 Serial Wire Debug Clock / GPIO HPD_P0/P2.0 GPIO F8 Hot Plug Detect I/O for Port-0 / GPIO I2C_SDA_SCB2/P2.1 GPIO E11 SCB2 data for configuring Re-timer or DP/USB Multi-Function MUX/ GPIO GPIOs and Serial Interfaces I2C_SCL_SCB2/P2.2 GPIO E10 SCB2 clock for configuring Re-timer or DP/USB Multi-Function MUX/ GPIO P2.3 GPIO E8 GPIO I2C_INT_TBT_P1/P0.5 GPIO H8 ThunderBolt interrupt for Port-1 / GPIO P2.5 GPIO D8 GPIO I2C_SCL_SCB0/P4.0 GPIO D11 SCB0 clock for communicating with Embedded controller / GPIO I2C_SDA_SCB0/P4.1 GPIO C11 SCB0 data for communicating with Embedded controller / GPIO P3.0 GPIO B10 GPIO I2C_SDA_SCB3/P3.1 GPIO B11 SCB3 data / GPIO I2C_SCL_SCB3/P3.2 GPIO B9 SCB3 clock / GPIO HPD_P1/P3.3 GPIO B8 Hot Plug Detect I/O for Port-1 / GPIO Reset XRES Analog C10 Reset input VBUS_C_P0 Power A1,A2,B1,B2,C1 Type-C VBUS Connector Input for Port-0 (4-V to 21.5-V) VBUS_C_P1 Power J1,K1,K2,L1,L2 Type-C VBUS Connector Input for Port-1 (4-V to 21.5-V) VBUS_P_P0 Power C2,D1,D2,E1,E2 VBUS Provider Input for Port-0 (4-V to 5.5-V) VBUS_P_P1 Power G1,G2,H1,H2,J2 VBUS Provider Input for Port-1 (4-V to 5.5-V) VSYS Power F4 2.75-V to 5.5-V supply for the system Power VDDD supply output VDDD Power G7 1. VSYS powered - (Min: VSYS-50 mV) 2.7 to 5.5 2. VBUS powered - 3.0 V to 3.6 V VDDIO Power F7 At system-level short the VDDD to VDDIO VCCD Power E7 1.8-V regulator output for filter capacitor. This pin cannot drive external load. V5V_P0 Power B4 4.85-V to 5.5-V supply for VCONN FET of Type-C: Port-0 V5V_P1 Power K4 4.85-V to 5.5-V supply for VCONN FET of Type-C: Port-1 D7, E5, E6, F1, Ground VSSD Ground F2, F5, F6, G4, Ground G5, G6 Document Number: 002-27161 Rev. *E Page 11 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support