Datasheet 8V97003 (IDT)

Описание171.875MHz to 18GHz RF / mmWave Wideband Synthesizer with Integrated VCO
Страниц / Страница66 / 1 — 171.875MHz to 18GHz RF / mmWave. 8V97003. Wideband Synthesizer with …
Размер файла1.3 Мб

171.875MHz to 18GHz RF / mmWave. 8V97003. Wideband Synthesizer with Integrated VCO. Datasheet. Description. Features

Datasheet 8V97003 IDT, Версия: 20200120

Модельный ряд для этого даташита

Текстовая версия документа

171.875MHz to 18GHz RF / mmWave 8V97003 Wideband Synthesizer with Integrated VCO Datasheet Description Features
The 8V97003 is a high-performance mmWave wideband ▪ Output frequency range: 171.875MHz to 18GHz Synthesizer / Phase Lock Loop (PLL) that generates output ▪ Ultra-low phase noise VCO frequencies up to 18GHz from an integrated Voltage Controlled • -60.6dBc integrated phase jitter (35fs rms jitter) from 20kHz Oscil ator (VCO) offering an octave of frequency tuning range. to 100MHz at 6GHz The device also offers a high-performance 32-bit fractional feedback divider and an output divider to al ow users to fully ▪ Figure of Merit: -236dBc/Hz benefit from the wideband characteristics of the VCO. ▪ Input reference frequency: • The device's figure of merit (FOM) of -236dBc/Hz and the 10MHz to 1.6GHz (LVPECL, LVDS) excellent VCO performance allow for very low phase noise and • 10MHz to 250MHz (LVCMOS) RMS phase jitter. ▪ Fractional-N synthesizer and integer-N synthesizer The 8V97003 offers a very low output-to-output phase skew drift ▪ 32-bit of fractional and modulus resolution of < 10° across al operating conditions and frequencies, reducing ▪ Phase frequency detector (PFD) operation up to 500MHz radio path recalibration occurrences in beamforming applications, (Integer mode) or 250MHz (Fractional mode) such as 5G radio card massive MIMO systems. ▪ Programmable RF output power levels The output drivers have programmable output power settings and ▪ RF output power < -80dBm when in MUTE can deliver high single-ended output power up of +12dBm at ▪ Programmable input multiplier (MULT) to increase PFD 8GHz, and +4dBm at 18GHz, when using inductively loaded frequency when using a low input frequency output terminations (double termination). When the outputs are ▪ -40°C to +95°C ambient temperature range; and up to +105°C resistively loaded, the output drivers can deliver a single-ended case temperature output power of +9.5dBm at 8GHz, and up to -2.5dBm at 12GHz. The output power can be further increased when using differential ▪ 3.3V single power supply operation outputs and measuring the output power differential y. ▪ 7 7 mm 48-VFQFPN package ▪ SPI interface is compatible with 1.8V logic and tolerant to 3.3V The 8V97003 relies on a single 3.3V power supply and offers low noise integrated LDOs for excellent power supply noise immunity. ▪ Supported in the Timing CommanderTM design tool
Typical Applications Simplified Block Diagram
▪ 5G millimeter wave wireless infrastructure Loop Filter ▪ Massive MIMO ▪ Phase Array Antennas and beam forming x2 2x RF Out ▪ Wireless backhaul Clock x2 ÷R PLL Input 0.171-18GHz ▪ ÷M0 Point-to-point and point-to-multipoint microwave links 16-Bit Integer + 32-Bit Fractional ▪ Satellites / VSATs SPI Registers ▪ Test equipment/instrumentation ▪ Clock generation ▪ High-speed RF converters sampling clocks ▪ Radar ©2020 Renesas Electronics Corporation 1 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History