Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 6

ОписаниеIEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII
Страниц / Страница213 / 6 — KSZ8463ML/RL/FML/FRL. BIU - Bus Interface Unit. MDI-X - Medium Dependent …
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KSZ8463ML/RL/FML/FRL. BIU - Bus Interface Unit. MDI-X - Medium Dependent Interface. Crossover

KSZ8463ML/RL/FML/FRL BIU - Bus Interface Unit MDI-X - Medium Dependent Interface Crossover

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KSZ8463ML/RL/FML/FRL BIU - Bus Interface Unit
The host interface function that performs code conversion, buffering, and the like required for communications to and from a network.
MDI-X - Medium Dependent Interface
An Ethernet port connection that allows networked end stations (i.e.,
PCs or workstations) to connect to each other using a null-modem, or crossover, cable. For 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter con- nects to the far end receiver. When connecting two computers together, a cable that crosses the TX and RX is required to do this. With auto MDI-X, the PHY senses the correct TX and RX roles, elim- inating any cable confusion.
MIB - Management Information Base
The MIB comprises the management portion of network devices. This can include things like monitoring traffic levels and faults (statis- tical), and can also change operating parameters in network nodes (static forwarding addresses).
MII - Media Independent Interface
The MII accesses PHY registers as defined in the IEEE 802.3 speci- fication.
NIC - Network Interface Card
An expansion board inserted into a computer to allow it to be con- nected to a network. Most NICs are designed for a particular type of network, protocol, and media, although some can serve multiple net- works.
The port VLAN ID value is used as a VLAN reference.
NRZ - Non-Return to Zero
A type of signal data encoding whereby the signal does not return to a zero state in between bits.
A device or functional block which performs the physical layer inter- face function in a network.
PLL - Phase-Locked Loop
An electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or ref- erence, signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency.
PTP - Precision Time Protocol
A protocol, IEEE 1588 as applied to this device, for synchronizing the clocks of devices attached to a specific network.
SA - Source Address
The address from which information has been sent.
TDR - Time Domain Reflectometry
TDR is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. They send a signal down the conductor and measure the time it takes for the signal, or part of the signal, to return.
TSU - time stamp Input Unit
The functional block which captures signals on the GPIO pins and assigns a time to the specific event.
TOU - Trigger Output Unit
The functional block which generates user configured waveforms on a specified GPIO pin at a specific trigger time.
UTP - Unshielded Twisted Pair
Commonly a cable containing four twisted pairs of wires. The wires are twisted in such a manner as to cancel electrical interference gen- erated in each wire, therefore shielding is not required.
VLAN - Virtual Local Area Network
A configuration of computers that acts as if all computers are con- nected by the same physical network but which may be located virtu- ally anywhere. DS00002642A-page 6

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
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