AD9361Data Sheet20–30ATT 0, –40°CATT 0, +25°CATT 0, +85°C–35Bc)ATT 25, –40°CATT 25, +25°CATT 25, +85°C16dATT 50, –40°CATT 50, +25°CATT 50, +85°C(–40UDE IT12)LmP–45dB (–40°C38+25°C–50+85°COIPBAND AMTXIDE–554S E L–60ING0S X–65T–4–70048121620 071 5.05.15.25.35.45.55.65.75.85.96.0 073 TX ATTENUATION SETTING (dB) 10453- FREQUENCY (GHz) 10453- Figure 71. TX Third-Order Output Intercept Point (OIP3) vs. Figure 73. TX Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset TX Attenuation Setting, fLO_TX = 5.8 GHz 150149148) 147Hz B/ d146NR ( S–40°CX 145T+25°C +85°C14414314203691215 072 TX ATTENUATION SETTING (dB) 10453- Figure 72. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset, fLO_TX = 5.745 GHz Rev. F | Page 32 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE