link to page 10 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The outputs of PCG A and B can be routed through the DAI The core timer can be configured to use FLAG3 as a timer pins and the outputs of PCG C and D can be driven on to the expired signal, and the general-purpose timers have one bidirec- DAI as well as the DPI pins. tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, Digital Peripheral Interface (DPI) a 32-bit period register, and a 32-bit pulse width register. A sin- The ADSP-2148x SHARC processors have a digital peripheral gle control and status register enables or disables the general- interface that provides connections to two serial peripheral purpose timer. interface ports (SPI), one universal asynchronous receiver- 2-Wire Interface Port (TWI) transmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two general-purpose timers. The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. Serial Peripheral (Compatible) Interface (SPI) The TWI master incorporates the following features: The SPI is an industry-standard synchronous serial link, • 7-bit addressing enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one • Simultaneous master and slave operation on multiple device select pin, and one clock pin. It is a full-duplex synchro- device systems with support for multi master data nous serial interface, supporting both master and slave modes. arbitration The SPI port can operate in a multimaster environment by • Digital filtering and timed event processing interfacing with up to four other SPI-compatible devices, either • 100 kbps and 400 kbps data rates acting as a master or slave device. The SPI-compatible periph- eral implementation also features programmable baud rate and • Low interrupt rate clock phase and polarities. The SPI-compatible port uses open I/O PROCESSOR FEATURES drain drivers to support a multimaster configuration and to avoid data contention. The I/O processors provide up to 65 channels of DMA, as well as an extensive set of peripherals. UART PortDMA Controller The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible The processor’s on-chip DMA controller allows data transfers with PC-standard UARTs. The UART port provides a simpli- without processor intervention. The DMA controller operates fied UART interface to other peripherals or hosts, supporting independently and invisibly to the processor core, allowing full-duplex, DMA-supported, asynchronous transfers of serial DMA operations to occur while the core is simultaneously exe- data. The UART also has multiprocessor communication capa- cuting its program instructions. DMA transfers can occur bility using 9-bit address detection. This allows it to be used in between the ADSP-2148x’s internal memory and its serial ports, multidrop networks through the RS-485 data interface the SPI-compatible (serial peripheral interface) ports, the IDP standard. The UART port also includes support for 5 to 8 data (input data port), the PDAP, or the UART. The DMA channel bits, 1 or 2 stop bits, and none, even, or odd parity. The UART summary is shown in Table 8. port supports two modes of operation: Programs can be downloaded to the ADSP-2148x using DMA • PIO (programmed I/O)—The processor sends or receives transfers. Other DMA features include interrupt generation data by writing or reading I/O-mapped UART registers. upon completion of DMA transfers and DMA chaining for The data is double-buffered on both transmit and receive. automatic linked DMA transfers. • DMA (direct memory access)—The DMA controller trans- fers both transmit and receive data. This reduces the Table 8. DMA Channels number and frequency of interrupts required to transfer PeripheralDMA Channels data to and from memory. The UART has two dedicated SPORTs 16 DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA IDP/PDAP 8 channels because of their relatively low service rates. SPI 2 UART 2 Timers External Port 2 The ADSP-2148x has a total of three timers: a core timer that Accelerators 2 can generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be Memory-to-Memory 2 independently set to operate in one of three modes: MLB1 31 • Pulse waveform generation mode 1 Automotive models only. • Pulse width count/capture mode • External event watchdog mode Rev. H | Page 10 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
