Datasheet AD5560 (Analog Devices) - 48

AD5560 Data Sheet Table 18. DPS Register 1 Address Default Data Bits, MSB First
0x2 0x0000
Bit Name Function
15 SW-INH This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the HW_INH hardware inhibit pin. 14 Reserved Reserved, set to 0. 13 I[2:0] Current range addressing. These bits allow selection of the required current range. 12 11
I Action
0 ±5 µA current range. 1 ±25 µA current range. 2 ±250 µA current range. 3 ±2.5 mA current range. 4 ±25 mA current range. 5 External Range 2. 6 External Range 1. 7 Reserved. 10 CMP[1:0] Comparator function. CMP1 acts as a comparator output enable, whereas CMP0 selects between a comparing DUT current or voltage; by default, the comparators are high-Z on power-on. 9
CMP Action
0 Comparator outputs high-Z. 1 Comparator outputs high-Z. 2 Compare DUT current. 3 Compare DUT voltage. 8 ME[3:0] Bits ME[3:0] allow selection of the required measure mode, allowing the MEASOUT line to be disabled; connect to the temperature sensor or enable it for measurement. ME[3] is MEASOUT enable/disable; when 7 high, MEASOUT is enabled, and ME[2:0] can be used to preselect the measuring parameter. Where a 6 number of MEASOUT lines are connected together and passed to a common ADC, this function can allow 5 for much faster measurement time between channels because the slew time of the measurement buffer is reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register.
ME[2:0] Action
0 MEASOUT high-Z. 1 Connect MEASOUT to ISENSE. 2 Connect MEASOUT to VSENSE. 3 Connect MEASOUT to KSENSE. 4 Connect MEASOUT to TSENSE. 5 Connect MEASOUT to DUTGND SENSE. 6 Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7). 7 Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7). 4 CLEN Clamp enable; set high to enable the clamp; set low to disable the clamp. This bit is OR’d with the hardware CLEN pin. 3:0 Unused Set to 0. Rev. E | Page 48 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE