LT1158 OPERATION (Refer to Functional Diagram) goes low in PWM operation, and is maintained by the charge comparator input pins 11 and 12 are normally connected pump when the top MOSFET is on DC. A regulated boost across a shunt in the source of the top power MOSFET driver at pin 1 employs a source-referenced 15V clamp (or to a current-sensing MOSFET). When pin 11 is more that prevents the bootstrap capacitor from overcharging than 1.2V below V+ and V12 – V11 exceeds the 110mV regardless of V+ or output transients. offset, FAULT pin 5 begins to sink current. During a short circuit, the feedback loop regulates V12 – V11 to 150mV, The LT1158 provides a current-sense comparator and fault thereby limiting the top MOSFET current. output circuit for protection of the top power MOSFET. The APPLICATIONS INFORMATION Power MOSFET Selection and the available heat sinking has a thermal resistance of 20°C/W, the MOSFET junction temperature will be 125°C, Since the LT1158 inherently protects the top and bottom and ∂ = 0.007(125 – 25) = 0.7. This means that the required MOSFETs from simultaneous conduction, there are no size R or matching constraints. Therefore selection can be made DS(ON) of the MOSFET will be 0.089Ω/1.7 = 0.0523Ω, which can be satisfi ed by an IRFZ34. based on the operating voltage and RDS(ON) requirements. The MOSFET BVDSS should be at least 2 • VSUPPLY, and Note that these calculations are for the continuous operating should be increased to 3 • VSUPPLY in harsh environments condition; power MOSFETs can sustain far higher dissipa- with frequent fault conditions. For the LT1158 maximum tions during transients. Additional RDS(ON)) constraints are operating supply of 30V, the MOSFET BVDSS should be discussed under Starting High In-Rush Current Loads. from 60V to 100V. The MOSFET RDS(ON) is specifi ed at TJ = 25°C and is gener- ally chosen based on the operating effi ciency required as GATE DR long as the maximum MOSFET junction temperature is not LT1158 R exceeded. The dissipation in each MOSFET is given by: G RG GATE FB 2 P =D I ( + 1 ∂ R ( ) DS ( ) DS ON RG: OPTIONAL 10Ω 1158 F01 where D is the duty cycle and ∂ is the increase in RDS(ON) at the anticipated MOSFET junction temperature. From this Figure 1. Paralleling MOSFETs equation the required RDS(ON) can be derived: Paralleling MOSFETs P R MOSFETs can be paralleled. The MOSFETs will inherently DS ON ( ) = 2 D I ( ) ( + 1 ∂) share the currents according to their RDS(ON) ratio. The DS LT1158 top and bottom drivers can each drive four power For example, if the MOSFET loss is to be limited to 2W MOSFETs in parallel with only a small loss in switching when operating at 5A and a 90% duty cycle, the required speeds (see Typical Performance Characteristics). Indi- RDS(ON) would be 0.089Ω/(1 + ∂). (1 + ∂) is given for vidual gate resistors may be required to “decouple” each each MOSFET in the form of a normalized RDS(ON) vs MOSFET from its neighbors to prevent high frequency temperature curve, but ∂ = 0.007/°C can be used as an oscillations—consult manufacturer’s recommendations. approximation for low voltage MOSFETs. Thus if TA = 85°C 1158fb 9
