Datasheet KSZ8864CNX, KSZ8864RMNUB (Microchip)

ПроизводительMicrochip
ОписаниеIntegrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
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KSZ8864CNX/RMNUB. Integrated 4-Port 10/100 Managed Switch with. Two MACs MII or RMII Interfaces. Features

Datasheet KSZ8864CNX, KSZ8864RMNUB Microchip

21 предложений от 10 поставщиков
IC: ethernet switch; 10/100Base-T; MDC,MDI,MDI-X,MDIO,MII,RMII
ЭИК
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KSZ8864CNXCA
от 245 ₽
Элитан
Россия
KSZ8864CNXC
Microchip
466 ₽
TMElectronics
Россия
KSZ8864CNXI
Microchip
от 679 ₽
KSZ8864CNXI
Microchip
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KSZ8864CNX/RMNUB Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces Features Advanced Switch Features QoS/CoS Packet Prioritization Support
• IEEE 802.1q VLAN Support for up to 128 VLAN • Per Port, 802.1p and DiffServ-Based Groups (Full-Range 4096 of VLAN IDs) • 1/2/4-Queue QoS Prioritization Selection • Static MAC Table Supports up to 32 Entries • Programmable Weighted Fair Queuing for Ratio • VLAN ID Tag/Untagged Options, Per Port Basis Control • IEEE 802.1p/q Tag Insertion or Removal on a Per • Re-Mapping of 802.1p Priority Field Per Port Port Basis Based on Ingress Port (Egress) Basis • Programmable Rate Limiting at the Ingress and
Integrated 4-Port 10/100 Ethernet Switch
Egress on a Per Port Basis • Next Generation Switch with Four MACs and Two • Jitter-Free Per Packet Based Rate Limiting PHYs that are Fully Compliant with the IEEE Support 802.3u Standard • Broadcast Storm Protection with Percentage • Non-Blocking Switch Fabric Ensures Fast Packet Control (Global and Per Port Basis) Delivery by Utilizing a 1K MAC Address Lookup • IEEE 802.1d Rapid Spanning Tree Protocol RSTP Table and a Store-and-Forward Architecture Support • On-Chip 64Kbyte Memory for Frame Buffering • Tail Tag Mode (1 Byte Added Before FCS) (Not Shared with 1K Unicast Address Table) Support at Port 4 to Inform the Processor Which • Full-Duplex IEEE 802.3x Flow Control (PAUSE) Ingress Port Receives the Packet with Force Mode Option • 1.4 Gbps High-Performance Memory Bandwidth • Half-Duplex Back Pressure Flow Control and Shared Memory Based Switch Fabric with • HP Auto MDI/MDI-X and IEEE Auto Crossover Fully Non-Blocking Configuration Support • Dual MII/RMII with MAC 3 SW3-MII/RMII and • LinkMD® TDR-Based Cable Diagnostics to Iden- MAC 4 SW4-MII/RMII Interfaces tify Faulty Copper Cabling • Enable/Disable Option for Huge Frame Size up to • MII Interface of MAC Supports Both MAC Mode 2000 Bytes Per Frame and PHY Mode • IGMP v1/v2 Snooping (IPv4) Support for Multicast • Per Port LED Indicators for Link, Activity, and 10/ Packet Filtering 100 Speed • IPv4/IPv6 QoS Support • Register Port Status Support for Link, Activity, • Support Unknown Unicast/Multicast Address and Full-/Half-Duplex and 10/100 Speed Unknown VID Packet Filtering • On-Chip Terminations and Internal Biasing • Self-Address Filtering Technology for Cost Down and Lowest Power
Comprehensive Configuration Register Access
Consumption • Serial Management Interface (MDC/MDIO) to All
Switch Monitoring Features
PHYs Registers • Port Mirroring/Monitoring/Sniffing: Ingress and/or • High-Speed SPI (up to 25 MHz) and I2C Master Egress Traffic to Any Port or MII/RMII Interface to all Internal Registers • MIB Counters for Fully Compliant Statistics Gath- • I/O Pins Strapping and EEPROM to Program ering 34 MIB Counters Per Port Selective Registers in Unmanaged Switch Mode • Loopback Support for MAC, PHY, and Remote • Control Registers Configurable on the Fly Diagnostic of Failure (Port-Priority, 802.1p/d/q, AN…) • Interrupt for the Link Change on Any Ports  2018 Microchip Technology Inc.

DS00002229D-page 1 Document Outline Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces 1.0 Introduction 1.1 General Description FIGURE 1-1: Functional Diagram 2.0 Pin Description and Configuration FIGURE 2-1: 64-QFN Pin Assignment (TOP View) TABLE 2-1: Signals - KSZ8864CNX/RMNUB TABLE 2-2: Strap-In Options - KSZ8864CNX/RMNUB 3.0 Functional Description 3.1 Physical Layer Transceiver 3.1.1 100BASE-TX Transmit 3.1.2 100BASE-TX Receive 3.1.3 PLL Clock Synthesizer 3.1.4 Scrambler/De-Scrambler (100BASE-TX Only) 3.1.5 10BASE-T Transmit 3.1.6 10BASE-T Receive 3.1.7 MDI/MDI-X Auto Crossover TABLE 3-1: MDI/MDI-X Pin Definitions FIGURE 3-1: Typical Straight Cable Connection FIGURE 3-2: Typical Crossover Cable Connection 3.1.8 Auto-Negotiation FIGURE 3-3: Auto-Negotiation Flow Chart 3.1.9 LinkMD® Cable Diagnostics 3.1.10 On-Chip Termination Resistors 3.2 Power Management TABLE 3-2: Internal Function Block Status 3.2.1 Normal Operation Mode 3.2.2 Energy Detect Mode 3.2.3 Soft Power-Down Mode 3.2.4 Power-Saving Mode 3.2.5 Port-Based Power-Down Mode 3.3 Switch Core 3.3.1 Address Look-Up 3.3.2 Learning 3.3.3 Migration 3.3.4 Aging 3.3.5 Forwarding 3.3.6 Switching Engine 3.3.7 Media Access Control (MAC) Operation 3.3.8 Inter-Packet Gap (IPG) 3.3.9 Back-Off Algorithm 3.3.10 Late Collision 3.3.11 Illegal Frames 3.3.12 Flow Control FIGURE 3-4: Destination Address Look-Up Flow Chart - Stage 1 FIGURE 3-5: Destination Address Resolution Flow Chart - Stage 2 3.3.13 Half-Duplex Back Pressure 3.3.14 Broadcast Storm Protection 3.3.15 MII Interface Operation 3.3.16 Switch MAC3/MAC4 SW3/SW4-MII Interface TABLE 3-3: Switch MAC3 SW3-MII and Mac4 SW4-MII Signals 3.3.17 Switch MAC3/MAC4 SW3/SW4-RMII Interface TABLE 3-4: MAC3 SW3-RMII and MAC4 SW4-RMII Connections 3.4 Advanced Functionality 3.4.1 QoS Priority Support FIGURE 3-6: 802.1p Priority Field Format 3.4.2 Spanning Tree Support 3.4.3 Rapid Spanning Tree Support 3.4.4 Tail Tagging Mode FIGURE 3-7: Tail Tag Frame Format TABLE 3-5: Tail Tag Rules 3.4.5 IGMP Support 3.4.6 Port Mirroring Support 3.4.7 VLAN Support TABLE 3-6: FID+DA Look Up in VLAN Mode TABLE 3-7: FID+SA Look Up in VLAN Mode 3.4.8 Rate Limiting Support 3.4.9 Ingress Rate Limit 3.4.10 Egress Rate Limit 3.4.11 Transmit Queue Ratio Programming 3.4.12 Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast 3.4.13 Configuration Interface FIGURE 3-8: EEPROM Configuration Timing Diagram 3.4.14 SPI Slave Serial Bus Configuration TABLE 3-8: SPI Connections FIGURE 3-9: SPI Write Data Cycle FIGURE 3-10: SPI Read Data Cycle FIGURE 3-11: SPI Multiple Write FIGURE 3-12: SPI Multiple Read 3.5 MII Management (MIIM) Interface TABLE 3-9: MII Management Frame Format 3.6 Serial Management Interface (SMI) TABLE 3-10: Serial Management Interface (SMI) Frame Format 4.0 Register Descriptions TABLE 4-1: Registers Descriptions 4.1 Global Registers TABLE 4-2: Global Register Descriptions 4.2 Port Registers TABLE 4-3: Port Registers 4.3 Advanced Control Registers TABLE 4-4: Advanced Control Register Descriptions TABLE 4-5: Data Rate Selection in 100BT TABLE 4-6: Data Rate Selection in 10BT 4.4 Static MAC Address Table TABLE 4-7: Format of Static MAC Table for Reads TABLE 4-8: Format of Static MAC Table for Writes 4.5 VLAN Table TABLE 4-9: VLAN Table TABLE 4-10: VLAN ID and Indirect Registers 4.6 Dynamic MAC Address Table TABLE 4-11: Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters TABLE 4-12: MIB Counters 4.8 MIIM Registers TABLE 4-13: MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics TABLE 6-1: Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing FIGURE 7-1: EEPROM Interface Input Receive Timing Diagram FIGURE 7-2: EEPROM Interface Output Transmit Timing Diagram TABLE 7-1: EEPROM Timing Parameters 7.2 MII Timing FIGURE 7-3: MAC Mode MII Timing - Data Received from MII FIGURE 7-4: MAC Mode MII TIming - Data Transmitted from MII TABLE 7-2: MAC Mode MII Timing Parameters FIGURE 7-5: PHY Mode MII Timing - Data Received from MII FIGURE 7-6: PHY Mode MII Timing - Data Transmitted from MII TABLE 7-3: PHY Mode MII Timing Parameters 7.3 RMII Timing FIGURE 7-7: RMII Timing - Data Received from RMII FIGURE 7-8: RMII Timing - Data Transmitted to RMII TABLE 7-4: RMII Timing Parameters 7.4 SPI Timing FIGURE 7-9: SPI Input TiminG FIGURE 7-10: SPI OUTput Timing TABLE 7-5: SPI Timing Parameters 7.5 Auto-Negotiation Timing FIGURE 7-11: Auto-Negotiation Timing TABLE 7-6: Auto-Negotiation Timing Parameters 7.6 MDC/MDIO Timing FIGURE 7-12: MDC/MDIO Timing TABLE 7-7: MDC/MDIO Typical Timing Parameters 7.7 Reset Timing FIGURE 7-13: Reset Timing Diagram TABLE 7-8: Reset Timing Parameters 8.0 Reset Circuit FIGURE 8-1: Recommended Reset Circuit FIGURE 8-2: Recommended Reset Circuit for CPU/FPGA Reset Output 9.0 Selection of Isolation Transformer, (Note 1) TABLE 9-1: Transformer Selection Criteria 9.0.1 Selection of Transformer Vendors TABLE 9-2: Qualified Magnetic Vendors 9.0.2 Selection of Reference Crystal TABLE 9-3: Typical Reference Crystal Characteristics 10.0 Package Outline FIGURE 10-1: 64-Lead QFN 8 mm x 8 mm Package The Microchip WebSite Customer Change Notification Service Customer Support Appendix A: Data Sheet Revision history Product Identification System AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - 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