Datasheet HIP2210, HIP2211 100V, 3A Source, 4A Sink, High Frequency Half-Bridge Drivers with HI/LI or Tri-Level PWM Input and Adjustable Dead Time The HIP2210 and HIP2211 are 100V, 3A source, 4A Features sink high-frequency half-bridge NMOS FET drivers. • HIP2211 drop-in replacement for the ISL2111 and The HIP2211 features standard HI/LI inputs and is HIP2101 8 Ld SOIC, 8 Ld DFN, and 10 Ld TDFN pin-compatible with popular Renesas bridge drivers packages such as the HIP2101 and ISL2111. The HIP2210 features a tri-level PWM input with programmable • 115VDC bootstrap supply maximum voltage dead time. Its wide operating supply range of 6V to supports 100V on the half-bridge 18V and integrated high-side bootstrap diode • 3A source and 4A sink gate drivers for NMOS FETs supports driving the high-side and low-side NMOS in 100V half-bridge applications. • Fast propagation delay and matching: 15ns typical delay; 2ns typical matching (HIP2211) These drivers feature strong 3A source, 4A sink drivers with very fast 15ns typical propagation delay • Integrated 0.5Ω typical bootstrap diode and 2ns typical delay matching, making it optimal for • Wide 6V to 18V operating voltage range high-frequency switching applications. VDD and boot • VDD and boot Undervoltage Lockout (UVLO) UVLO protects against an undervoltage operation. • Robust noise tolerance: wide hysteresis at inputs; The tri-level input of the HIP2210 PWM pin controls HS pin tolerates up to -10V continuous the high-side and low-side drivers with a single pin. When the PWM input is at logic high, the high-side • HIP2211: HI/LI inputs 3.3V logic compatible with bridge FET is turned on and the low-side FET is off. VDD voltage tolerance When the input is at logic low, the low-side bridge FET • HIP2210: Tri-Level PWM input with logic threshold is turned on and the high-side FET is turned off. When levels set by external VREF pin from 2.7V to 5.5V the input voltage is in the mid-level state, both the • HIP2210: Programmable dead time prevents high-side and low-side bridge FETs are turned off. shoot-through; adjustable from 35ns to 350ns with a The PWM threshold levels are proportional to an single resistor external input reference voltage on the VREF pin, allowing PWM operation across a 2.7V to 5.5V logic Applications range. • Telecom half-bridge and full-bridge DC/DC The HIP2210 is offered in a 10 Ld 4x4mm TDFN converters package. The HIP2211 is offered in 8 Ld SOIC, 8 Ld 4x4mm DFN, and 10 Ld 4x4mm TDFN packages.
• 3-phase BLDC motor driver; H-Bridge motor driver • Two-switch forward and active clamp converters Related Literature • Multiphase PWM DC/DC controllers For a full list of related documents, visit our website: • Class-D amplifiers • HIP2210, HIP2211 device pages 12V12V1 VDDVCCVDD100 V100VHBVREFHBVCC2HOHO3ENHIPWM5HSPWMPWMHIP2210HSHIP 22114VOUTVOUTDC/DCController10 Ld DFNControllerLILOLO68RDTVSSVSS7VSSVSSHIP2211 Pin-to-Pin Compatible with IS L21 11HIP 2210 PWM Input with Programmble Dead TimeFigure 1. HIP2211 HI/LI Input Bridge Driver TypicalFigure 2. HIP2210 PWM Input Bridge Driver TypicalApplicationApplication FN9347 Rev.1.01 Page 1 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings