MLX75026 QVGA Time-of-Flight Sensor PRELIMINARY DATASHEET 5.2. MIPI Alliance CSI-2 Description This section describes a limited set of CSI-2 functionality needed to understand operation of MLX75026. For a full interface description, please refer to MIPI Alliance CSI-2 Specification version 1.20. 5.2.1. Packet Structure CSI-2 uses a byte oriented, packet based protocol that supports the transport of arbitrary data using Short Package (SP) and Long Package (LP) formats. A 32bit Short Packet does not have any data or a Package Footer (PF). Only FS (Frame Start) or FE (Frame End) indicators use Short Packets. Long Packet Short Packet ... LPS PH PF SoT Data EoT LPS ... Package Header Package Footer 16bit 16bit WC CS DataID ECC Word Count Error Correction Code Checksum 8bit VC DT Virtual Channel Data Type 2bit 6bit Figure 18: Package structure Every packet starts with a SoT (start of transmission) sequence preceded by a LPS (low power state). An EoT (end of transmission) sequence followed by the low power state indicates the end of a packet. Each byte is transmitted with the least significant bit first, in case of multi-byte data (such as WC or CS) the least significant byte will be transmitted first, unless otherwise specified by the data format. VC: The virtual channel identifier provides separate channels for different data flows that are interleaved in the data stream (lane indicator). The default value is 0. DT: The data type value specifies the format and content of the data payload. 0x00 = FS (Frame Start) 0x12 = Embedded data (or MetaData) 0x01 = FE (Frame End) 0x2C = RAW12 pixel data WC: For short packets the word count field is considered a 16bit data field, representing the Frame Count [7:0]. After each FS (Frame Start) transmission, the Frame Count will be increased by 1. For long packets word count specifies the total amount of bytes between the end of PH and start of PF. ECC: The error correction code used is a 7+1bits Hamming-modified code. This code allows single-bit errors to be corrected and 2-bit errors to be detected in the DataID and WC fields but is not capable of doing both simultaneously. CS: To detect possible errors in the data transmission, a checksum is calculated over each data packet. The checksum is a 16bit CRC generated by this polynomial: 𝐶𝑅𝐶 = 𝑥16 + 𝑥12 + 𝑥5 + 𝑥0 When WC is zero, CS will be 0xFFFF Preliminary Datasheet v0.5 Page 23 of 64 Document Outline Table of Contents Document Revision History Ordering Information 1. System Architecture 2. Sensor Block Diagram 3. Electrical Specifications 3.1. Absolute Maximum Ratings 3.2. Typical Operating Conditions 3.3. Video Interface 3.3.1. MIPI DC specification 3.3.2. MIPI AC specification 3.4. Power Consumption 3.5. Maximum Distance Frame Rate 3.6. Decoupling Recommendations 3.7. Power-up Sequence 3.8. Input Clock Requirements 3.9. I2C Specifications 4. Optical Characteristics 4.1. QVGA Pixel Array Configuration 4.2. Pixel & Image Array Characteristics 4.3. CRA (Chief Ray Angle) 4.4. MTF (Modulation Transfer Function) 4.5. Application Lens Design Recommendations 5. Communication Interface(s) 5.1. I2C (Inter-Integrated Circuit) 5.1.1. I2C Timing Sequence 5.1.2. Single I2C Read 5.1.3. Sequential I2C Read 5.1.4. Single I2C Write 5.1.5. Sequential I2C Write 5.1.6. I2C Slave Address 5.2. MIPI Alliance CSI-2 Description 5.2.1. Packet Structure 5.2.2. Data Format RAW12 5.2.2.1. Data Format in 4 Lane MIPI Configuration 5.2.2.2. Data Format in 2 Lane MIPI Configuration 6. Start-up Sequence 6.1. Initialization Process 6.2. Initialization Register Map 7. Register Settings 7.1. Video Output Configuration 7.2. Modes of Operation 7.3. Data Output Modes 7.4. HMAX & Frame Read-Out Time 7.4.1. PLLSSETUP 7.4.2. PRETIME 7.4.3. RANDNM0 7.5. PARAM_HOLD 7.6. USER_ID Register 7.7. Modulation Frequency 7.8. Frame Structure & Frame Rate 7.9. FRAME_STARTUP 7.10. FRAME_TIME 7.11. PHASE_COUNT 7.12. Px_PREHEAT, Px_PREMIX 7.13. Px_INTEGRATION 7.14. Px_PHASE_SHIFT 7.15. Px_PHASE_IDLE (or V-blanking) 7.16. Px_LEDEN 7.17. Px_DMIX0, Px_DMIX1 & Px_STATIC_LED 7.18. Analog Delay Setting 7.18.1. Coarse Delay 7.18.2. Fine Delay 7.18.3. Super Fine 7.19. Pixel Binning 7.20. Region of Interest (ROI) 7.21. Flip & Mirror 7.22. Temperature Sensor 7.23. Pixel & Phase Statistics 7.24. PN9 Test Pattern 7.25. Duty Cycle Adjustment 7.26. Illumination Signal (subLVDS or CMOS) 8. MetaData Description 8.1. Embedded Data Format in 4 Lane MIPI Configuration 8.2. Embedded Data Format in 2 Lane MIPI Configuration 9. Distance & Amplitude Calculation 10. Package Outline 10.1. Pinout & Equivalent I/O Circuitry 10.2. Mechanical Dimensions 10.3. PCB Landing Pattern & Layout Recommendations 10.4. Package Marking 10.5. Cover Tape Removal Disclaimer
