Datasheet ON Semiconductor FDV302P

October 2017 FDV302P
Digital FET, P-Channel
General Description Features This P-Channel logic level enhancement mode field effect
transistor is produced using our proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors.
Since
bias resistors are not required, this one P-channel FET can
replace several digital transistors with different bias resistors
such as the DTCx and DCDx series. -25 V, -0.12 A continuous, -0.5 A Peak.
RDS(ON) = 13 Ω @ VGS= -2.7 V
RDS(ON) = 10 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Replace many PNP digital transistors (DTCx and DCDx)
with one DMOS FET. SOT-23 SuperSOTTM-8 SuperSOTTM-6 SO-8 SOIC-16 SOT-223 Mark:302 D S G Absolute Maximum Ratings TA = 25oC unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm) -Continuous …