Application Note «Fault-Tolerant Analog Switches» (Maxim) - 4

Figure 3. To see how the circuit works, again assume the same +25V and -25V inputs. These voltages represent fault conditions, so the new circuit should both prevent those faults from coupling through the switch and keep the faults from damaging the chip itself. Taking the -25V case first, N1 sees -25V at its source, as does one input of the N3 sense switch. This sense circuit compares the (-25V) input to its -15V reference. Because the input exceeds -15V in the negative direction, N3 shorts it to the gate of N1, causing N1's Vgs to equal 0V; with no enhancement, N1 turns off. Concurrently, the comparator circuit with its -15V reference causes the n-channel driver to float; this cross-couples to the p-channel driver, causing the P1 gate to go to +15V (off condition). With both N1 and P1 turned off, the -25V fault cannot couple through the switch, and, as there is no possibility of forward-biased diode current from the input terminal, only minimal leakage currents flow. When the comparator senses a negative-voltage fault, its output turns on the N2 clamp circuit. This shorts the output terminal to -15V through a 1kΩ resistor (the value actually varies with the part number), a feature that is quite convenient for ADC applications. For the opposite polarity fault of +25V at the input, the P1, P3, and P2 stages work in a similar way, turning off both P1 and N1 and preventing anything other than leakage currents from flowing. For this overvoltage case, P2 clamps the output to +15V through, again, approximately 1kΩ. This scheme meets both our criteria: The fault doesn't couple through the switch, and the switch doesn't incur any power-related damage. The design combines the advantages of parallel FETs (low on- resistance and Rail-to-Rail signal handling) and series FETs (the part protects itself and doesn't couple Page 4 of 8 Document Outline maxim-ic.com Fault-Tolerant Analog Switches - Application Note - Maxim